collapse block in verilog

[tonylin]

Just downloaded and trying 18.0.1.2 32bit on win8.1.
"collapse block" in verilog seem not working properly.
It can detect begin/end, module/endmodule. But not collapse correctly.

Is it a known bug?

[Lee]

Can you provide an example and description of how it is not working correctly?

[tonylin]

// synopsys translate_off
module   colorBarTB;   // 纯粹为了保存彩条数据
reg   [7:0] colorBar[0:7];
initial begin
   colorBar[7] = {3'b111, 3'b111, 2'b11};      // white
   colorBar[6] = {3'b111, 3'b111, 2'b00};      // yellow
   colorBar[5] = {3'b000, 3'b111, 2'b11};      // cyan
   colorBar[4] = {3'b000, 3'b111, 2'b00};      // green
   colorBar[3] = {3'b111, 3'b000, 2'b11};      // maganta
   colorBar[2] = {3'b111, 3'b000, 2'b00};      // red
   colorBar[1] = {3'b000, 3'b000, 2'b11};      // blu
   colorBar[0] = {3'b000, 3'b000, 2'b00};      // black
end
endmodule
// synopsys translate_on

When collapse initial, endmodule is gone.
When collapse module, nothing happens.

Don't know how to send screen capture.

[tonylin]

Seems not that simple. I tried to copy it to a new file and it behaves differently. module is collapsed, but initial is not.

please give your email address and I can send you the whole file. And other files with other problems.

[Lee]

It does look like the initial block is hiding too many lines, I will have to look into that.  I do not have any issues with the module block.  If you wish to send files, you can open a support case and send them through there.