SV tagger not following parameterized base classes.

[warnerrs]

If the base class is defined by a parameter, the tagger doesn't follow the class hierarchy. This problem existed in VS18 as well. UVM uses this pattern extensively in the TLM portion of the library. Test case and screen shot attached.

-Ryan

[Lee]

Thanks for the report and an excellent test case.  That is a current limitation in the tagging lookup for SystemVerilog.  I will file this report in our feature tracker and we will try address in a future release.