B5: Slickedit Crashed when switching workspaces, won't relaunch

[tim_k]

I switched from one workspace to another using the pick list from the Project menu. It seemed to close the current project, and maybe started to load the new one, but vaporized before it completed the load. Now it vaporizes on every launch attempt:

/opt/slickedit/bin/vs: line 38:  6164 Segmentation fault      (core dumped) "$VS_LAUNCH_BIN_PATH/$VS_LAUNCH_BIN_NAME"_exe "$@"
I can't find the path it's referring to, so don't know where the dump is.

While writing this, I tried renaming the .slickedit/19.0.0 folder, forcing a re-creation/migration from 18.0.1 and now it will launch.
I kept the offending 19.0.0 folder so if you have a file I should look at for more info, let me know and I'll retrieve it.

-Tim

Here's  the system info:

SlickEdit 2014 (v19.0.0.8 64-bit)
Serial number: FE56917_BETA
License type: Beta License
License expiration: 2014-11-02 02:36:00
License file: /opt/slickedit/bin/slickedit.lic

Build Date: September 16, 2014
Emulation: CUA

OS: Linux
OS Version: Red Hat Enterprise Linux Workstation release 6.5 (Santiago)
Kernel Level: 2.6.32-431.29.2.el6.x86_64
Build Version: #1 SMP Sun Jul 27 15:55:46 EDT 2014
Processor Architecture: x86_64
X Server Vendor: Red Hat, Inc.
Memory: 33% Load, 4874MB/14632MB Virtual
Shell Info: /bin/csh -i
Screen Size: 2556 x 1363
Project Type: Verilog: Model Technology ModelSim
Language: .v (Verilog)
Installation Directory: /opt/slickedit/

[tim_k]

Update: After a normal quit, Slickedit started crashing on launch. Same error message as before. Some digging found the vrestore.slk file is the culprit. Removing that file from the .slickedit/19.0.0/ directory resolves the problem.

[Dan]

Can you post the offending vrestore.slk?

[tim_k]

I did a bit more digging, and discovered that the crash was because I've got Slickedit set to open the last workspace on launch. The .vtg file in that workspace is what was causing the problem. I removed the tag file and slickedit didn't crash. Put the tag file back and it did. Unfortunately the project I'm working on is export controlled, so I can't release the tag file.

If it helps, the workspace has 2 projects, with Verilog, SystemVerilog, VHDL, and TCL sources.

-Tim