Here's a concise example. The symbols that are correctly colored/tagged are the module name 'test' , the input port 'reset_n', and the internal signal 'internalWord'. Nothing else is correctly handled. In 18.0.3.3, all are correctly tagged/colored. Language keywords seem to be OK.
-Tim
Example:
`timescale 1ps/1ps
module test
(
input logic clock,
input logic reset_n,
input logic [15:0] inputA,
input logic [15:0] inputB,
output logic [15:0] outputA,
output logic validOut
)
logic [31:0] internalWord;
// flops
always_ff @(posedge clock, negedge reset_n)
begin
if (!reset_n)
begin
outputA <= '0;
end
else
begin
outputA <= inputA && inputB;
end
end
endmodule