Author Topic: SystemVerilog macro expansion and the tagger  (Read 1747 times)

warnerrs

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SystemVerilog macro expansion and the tagger
« on: October 05, 2014, 01:11:17 am »
Slick does not have a preprocessor configuration for SystemVerilog like it does for C++. There are a handful of macros in UVM which generate class member,s that I'd like the tagger to be able to parse.

Would it be possible to use a SlickC macro to do a substitution just before the tagger processes a file, and then undo that substitution right afterwards?