System Verilog - "Go to Definition" goes to the wrong line for ports/params

[tim_k]

Right click on either a parameter name, or a port name in the module and select "Go to Definition of <symbol name>". The cursor jumps to somewhere in the appropriate region (ports or parameters), but not the correct line. Signals and parameters defined within the module work fine - "Go to Definition" goes to the correct line. The problem exists on both Mac and Linux versions.

-Tim

[Lee]

I think I have an idea on this one, but could I have a sample that reproduces what you are seeing to confirm?

[tim_k]

This one reproduces the parameter failure, but not the port. Use parameterB on line 12. Both parameterA and parameterB go to the parameterA line. Everything else seems to work. I can try a more thorough example if necessary.

-Tim

-----------------------------------------------------------------
module reproTest
  #(
    parameter parameterA = 0,
    parameter parameterB = 1
  )
  (
    input   logic   inputA,
    input   logic   inputB,
    output  logic outputA
    );
 
  localparam localparamA = parameterA + parameterB;
 
  logic[localparamA:0]       moduleSignal;
 
 
 
  // ******************************************************************************
  //
  // ******************************************************************************
  always_ff @(posedge inputA, negedge inputB)
  begin
    if (!inputB)
      begin
        moduleSignal <= 0;
      end
    else
      begin
        moduleSignal <= {moduleSignal [1:0], inputA && inputB};
        outputA <= moduleSignal[localparamA];
      end
  end
endmodule

[Lee]

Thanks for the example.  This will be fixed in next beta drop.

[tim_k]

Nice! Thanks.

-Tim

[tim_k]

RC1 seems to have fixed this one.

-Tim