How can I modify the begin/end style formatting for Verilog files?
In the SlickEdit options for "All Languages"->Formatting I can see begin/end "Style 3" which is exactly what we use (only in Verilog). This pane shows C style syntax:
if()
{
++i
}
However in the Verilog language options, I don't see a similar setting, and certainly SlickEdit seems to automatically insert "Style 2" indents:
if (condition)
begin
out = in;
end
Is it possible for me to modify this syntax indent style?