Author Topic: SystemVerilog interface beautification  (Read 1278 times)

warnerrs

  • Senior Community Member
  • Posts: 114
  • Hero Points: 4
SystemVerilog interface beautification
« on: September 23, 2015, 07:13:13 pm »
Code inside SystemVerilog interfaces does not beautify.

Code: [Select]
interface irq_if;
logic irq_n;
task test;
endtask
modport master(output irq_n);
modport slave(input irq_n);
endinterface

warnerrs

  • Senior Community Member
  • Posts: 114
  • Hero Points: 4
Re: SystemVerilog interface beautification
« Reply #1 on: September 23, 2015, 07:18:34 pm »
Packages have the same problem.

Code: [Select]
package Vip;
integer x;
class UseRif;
    virtual reg_if rif;
endclass
endpackage

patrick

  • SlickEdit Team Member
  • Senior Community Member
  • *
  • Posts: 960
  • Hero Points: 72
Re: SystemVerilog interface beautification
« Reply #2 on: September 23, 2015, 07:24:00 pm »
I'm taking a look at it, thanks for the report.

patrick

  • SlickEdit Team Member
  • Senior Community Member
  • *
  • Posts: 960
  • Hero Points: 72
Re: SystemVerilog interface beautification
« Reply #3 on: September 23, 2015, 08:09:27 pm »
Fixed for the next release.  It looks like I made the same mistake for 'primitive' declarations as well, so I'll fix that for the next release as well.