Archived Read Only Forums > SlickEdit 2015 v20 Beta Discussion

SystemVerilog interface beautification

(1/1)

warnerrs:
Code inside SystemVerilog interfaces does not beautify.


--- Code: ---interface irq_if;
logic irq_n;
task test;
endtask
modport master(output irq_n);
modport slave(input irq_n);
endinterface

--- End code ---

warnerrs:
Packages have the same problem.


--- Code: ---package Vip;
integer x;
class UseRif;
    virtual reg_if rif;
endclass
endpackage

--- End code ---

patrick:
I'm taking a look at it, thanks for the report.

patrick:
Fixed for the next release.  It looks like I made the same mistake for 'primitive' declarations as well, so I'll fix that for the next release as well.

Navigation

[0] Message Index

Go to full version