Author Topic: SystemVerilog interface beautification  (Read 4692 times)

warnerrs

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SystemVerilog interface beautification
« on: September 23, 2015, 07:13:13 PM »
Code inside SystemVerilog interfaces does not beautify.

Code: [Select]
interface irq_if;
logic irq_n;
task test;
endtask
modport master(output irq_n);
modport slave(input irq_n);
endinterface

warnerrs

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Re: SystemVerilog interface beautification
« Reply #1 on: September 23, 2015, 07:18:34 PM »
Packages have the same problem.

Code: [Select]
package Vip;
integer x;
class UseRif;
    virtual reg_if rif;
endclass
endpackage

patrick

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Re: SystemVerilog interface beautification
« Reply #2 on: September 23, 2015, 07:24:00 PM »
I'm taking a look at it, thanks for the report.

patrick

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Re: SystemVerilog interface beautification
« Reply #3 on: September 23, 2015, 08:09:27 PM »
Fixed for the next release.  It looks like I made the same mistake for 'primitive' declarations as well, so I'll fix that for the next release as well.