Author Topic: SystemVerilog beautification of variable declarations  (Read 632 times)

warnerrs

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SystemVerilog beautification of variable declarations
« on: September 23, 2015, 07:16:35 pm »
Beautify does not make the following code pretty. Vector ranges and variable names should be in columns.

Code: [Select]
module dut(reg_if rif, irq_if irq, input logic evt);

    // 0: 31:8 = Load Value, 7:1 = Reserved, 0 = Enable
    // 1: 31:12 = Reserved, 11 = Reload on event, 10 = Pause on event, 9 = Disable on event, 8 = Irq on event, 7:2 = Reserved, 1 = Disable on timeout, 0 = Irq on timeout
    // 2: 31:8 = Value, 7:4 = Reserved, 3 = Reloaded, 2 = Paused, 1 = Enabled, 0 = Event Value
    logic[23:0] load_value;
    logic        enable;
    logic    event_reload;
    logic         event_pause;
    logic         event_disable;
    logic         event_irq;
    logic         timeout_disable;
    logic         timeout_irq;
    logic[24:0] cur_value;
    logic        reloaded;
    logic        paused;
    logic        enabled;
    logic        event_value;
module

patrick

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Re: SystemVerilog beautification of variable declarations
« Reply #1 on: September 30, 2015, 02:44:23 pm »
I cut it too close on this one, so this is not in beta 2.  But I'm doing cleanup and testing on it now, so expect it in the next drop.