Author Topic: System Verilog Beautification: Code alignment  (Read 827 times)

cng18.1970

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System Verilog Beautification: Code alignment
« on: October 06, 2015, 02:37:40 am »
Beautify does not align code in columns for the following cases:

1. Module port declarations: parameter declarations, input/output declarations, trailing comments
2. Variable declarations: names and vector and trailing comments
3. Assignments: Example : LHS "<=" RHS; All "<=" in a group a statements should be aligned in a tabular format. LHS/RHS lined up and aligned left.
4. Module instances: If named connectivity the all ".portname(wire)," should be aligned.



patrick

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Re: System Verilog Beautification: Code alignment
« Reply #1 on: October 06, 2015, 04:28:52 pm »
#2 is in for the next beta drop.  I'll take a look at the other cases you list.  Thanks for the feedback.