Author Topic: RC4 - System Verilog Beautify selection - really broken  (Read 1079 times)

tim_k

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RC4 - System Verilog Beautify selection - really broken
« on: October 30, 2015, 08:05:49 pm »
Start with this:

          if (roiEnable)
            begin
              if (roiLoad)
                begin
                  roiFrameBuffer0StartAddr  <= frameBuffer0StartAddr + roiStartOffset;
                  roiFrameBuffer1StartAddr  <= frameBuffer1StartAddr + roiStartOffset;
                  roiFrameBuffer2StartAddr  <= frameBuffer2StartAddr + roiStartOffset;
                  roiFrameBuffer3StartAddr  <= frameBuffer3StartAddr + roiStartOffset;
                end
            end
          else
            begin
              roiFrameBuffer0StartAddr  <= frameBuffer0StartAddr;
              roiFrameBuffer1StartAddr  <= frameBuffer1StartAddr;
              roiFrameBuffer2StartAddr  <= frameBuffer2StartAddr;
              roiFrameBuffer3StartAddr  <= frameBuffer3StartAddr;
            end

Select it, then beautify with the default, or modified formatting. Get this:

        if(roiEnable)
        begin
        if(roiLoad)
        begin
        roiFrameBuffer0StartAddr  <= frameBuffer0StartAddr + roiStartOffset;
        roiFrameBuffer1StartAddr  <= frameBuffer1StartAddr + roiStartOffset;
        roiFrameBuffer2StartAddr  <= frameBuffer2StartAddr + roiStartOffset;
        roiFrameBuffer3StartAddr  <= frameBuffer3StartAddr + roiStartOffset;
        end
        end
        else
        begin
        roiFrameBuffer0StartAddr  <= frameBuffer0StartAddr;
        roiFrameBuffer1StartAddr  <= frameBuffer1StartAddr;
        roiFrameBuffer2StartAddr  <= frameBuffer2StartAddr;
        roiFrameBuffer3StartAddr  <= frameBuffer3StartAddr;
        end

It doesn't matter what I do to the beautify format options, I always get this. If I beautify an entire file, it works fine.
Same behavior on Mac or Linux.

-Tim

patrick

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Re: RC4 - System Verilog Beautify selection - really broken
« Reply #1 on: October 30, 2015, 08:20:28 pm »
Reproduced it, I'm taking a look at it.  Thanks for the report.

tim_k

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Re: RC4 - System Verilog Beautify selection - really broken
« Reply #2 on: October 30, 2015, 09:08:05 pm »
Wow, that was fast.

While you're at it, this doesn't change if beautified as a selection:

      localRoiEnable             <= roiEnable;
      localRoiStartLine     <= roiStartLine;
      localRoiStartPix           <= roiStartPix;
      localRoiWidth          <= roiWidth;
      localRoiHeight             <= roiHeight;


But as a file beautifiy it gets fixed to this:

      localRoiEnable             <= roiEnable;
      localRoiStartLine          <= roiStartLine;
      localRoiStartPix           <= roiStartPix;
      localRoiWidth              <= roiWidth;
      localRoiHeight             <= roiHeight;


-Tim

patrick

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Re: RC4 - System Verilog Beautify selection - really broken
« Reply #3 on: October 30, 2015, 09:20:36 pm »
Yeah, I introduced a bug at a high level for the beautification of selections, so there aren't many selections that will do the right thing.  On the good side, it's easy enough to fix, I'm testing the fix now...

patrick

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Re: RC4 - System Verilog Beautify selection - really broken
« Reply #4 on: November 04, 2015, 02:43:56 pm »
Fixed in rc5.

tim_k

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Re: RC4 - System Verilog Beautify selection - really broken
« Reply #5 on: November 04, 2015, 10:48:54 pm »
Better, but not quite there for my purposes.
Snippet (already manually beautified):

          begin
            fieldID               <= 0;
            hBlank                <= 0;
            vBlank                <= 0;
            trsDecodeState        <= waitForTrs;
            pixelCounter          <= 0;
            lineCounter           <= 0;
            statusLineCount       <= 0;
            statusPixelCount      <= 0;
            fidToFrameBuff        <= 0;
            fieldSyncToFrameBuff  <= 0;
          end


If i select between the begin/end, but not including them and beautify I get this:

          begin
            fieldID <= 0;
            hBlank <= 0;
            vBlank <= 0;
            trsDecodeState <= waitForTrs;
            pixelCounter <= 0;
            lineCounter <= 0;
            statusLineCount <= 0;
            statusPixelCount <= 0;
            fidToFrameBuff <= 0;
            fieldSyncToFrameBuff <= 0;
          end


If I include the begin/end in the selection I get this:

        begin
            fieldID              <= 0;
            hBlank               <= 0;
            vBlank               <= 0;
            trsDecodeState       <= waitForTrs;
            pixelCounter         <= 0;
            lineCounter          <= 0;
            statusLineCount      <= 0;
            statusPixelCount     <= 0;
            fidToFrameBuff       <= 0;
            fieldSyncToFrameBuff <= 0;
        end


It's clearly not aligning the assignments in the first case.

-Tim

patrick

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Re: RC4 - System Verilog Beautify selection - really broken
« Reply #6 on: November 05, 2015, 02:37:22 pm »
Reproduced.  The alignment is implemented by a state machine, and it looks like the code that should ensure transitions to the final state for snippets does not. For the cases that work, its the following syntax (like the 'end') that get it into the final state.  Good catch.

patrick

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Re: RC4 - System Verilog Beautify selection - really broken
« Reply #7 on: November 09, 2015, 02:56:46 pm »
This is fixed for the 2015 point release.  Thanks for the report.