In code blocks for module instatiations, the beautifier puts the parenthesis for the assigned signal right up against the port name. It's common practice to align the left parens away from the port names, but the beautifier doesn't have this option.
Eg:
Beautifier:
avalonMaster
#(
// avalon MM master port
.avmSymbolWidth (avmSymbolWidth),
.avmNumSymbols (avmNumSymbols),
.avmAddressWidth (avmAddressWidth),
.avmBurstCountWidth (avmBurstCountWidth),
)
u_avalonMaster
(
.reset_n(reset_n),
.avmClk(avmClk),
.avmWaitRequest(avmWaitRequest),
.avmReadDataValid(avmReadDataValid),
.avmReadData(avmReadData),
.avmWrite(avmWrite),
.avmRead(avmRead),
.avmAddress(avmAddress),
.avmBurstCount(avmBurstCount),
.avmWriteData(avmWriteData),
);
Preferred:
avalonMaster
#(
// avalon MM master port
.avmSymbolWidth (avmSymbolWidth),
.avmNumSymbols (avmNumSymbols),
.avmAddressWidth (avmAddressWidth),
.avmBurstCountWidth (avmBurstCountWidth),
)
u_avalonMaster
(
.reset_n (reset_n),
.avmClk (avmClk),
.avmWaitRequest (avmWaitRequest),
.avmReadDataValid (avmReadDataValid),
.avmReadData (avmReadData),
.avmWrite (avmWrite),
.avmRead (avmRead),
.avmAddress (avmAddress),
.avmBurstCount (avmBurstCount),
.avmWriteData (avmWriteData),
);
-Tim
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