Very common in SystemVerilog is defining classes in macros like this:
`define rvm_export_suffix( SUFFIX ) \
class rvm_export``SUFFIX#( type TARGET=rvm_export_base ) extends rvm_export_base; \
function new(string name = "", rvm_component parent = null); \
super.new(name,parent); \
endfunction \
virtual function void write( rvm_object obj ); \
TARGET tgt; \
$cast(tgt, m_parent); \
tgt.write``SUFFIX( obj ); \
endfunction \
endclass
After beautification, it looks like this:
`define rvm_export_suffix( SUFFIX ) \
class rvm_export``SUFFIX#( type TARGET=rvm_export_base ) extends rvm_export_base; \
function new(string name = "", rvm_component parent = null); \
super.new(name,parent); \
endfunction \
virtual function void write( rvm_object obj ); \
TARGET tgt; \
$cast(tgt, m_parent); \
tgt.write``SUFFIX( obj ); \
endfunction \
endclass