Author Topic: RC5 - SystemVerilog syntax coloring  (Read 588 times)

tim_k

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RC5 - SystemVerilog syntax coloring
« on: November 05, 2015, 12:23:25 am »
It's been like this forever, but since you guys are spending a lot of time on SV right now (HUGE thanks BTW), I figured I'd add to the pile.

Every label or module instantance name is colored as if it were an undefined symbol. EG:


myModule
#(parameters list)
myModule_instanceName
(port list);


myModule_instanceName is colored red as "symbol not found" - as indicated by the popop when I hover over it.

Similarly, an always block with a label:


  always_ff @(posedge videoSyncClk, negedge reset_n)
    begin: frameSyncGenProc
        ........
    end: frameSyncGenProc


frameSyncGenProc is colored "symbol not found"

It would be nice if SlickEdit could identify labels and color them accordingly.

Oh, and while I'm on the subject, SlickEdit could use a little refinement in identifying `define symbols when they're used.
In a module if I've made a `define of a symbol:

`define videoSourceWidth              11'd640


Then use it in a module:

        registerCommand.writeData[0]     = {`videoSourceWidth};


`videoSourceWidth is colored as a `define, but so is videoSourceWidth (without the`). In SV these are NOT the same symbol. Having the same color for both makes it really hard to find the missing ` .

Thanks,

Tim

Clark

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Re: RC5 - SystemVerilog syntax coloring
« Reply #1 on: November 05, 2015, 03:28:18 am »
Thanks for the suggestions. Glad you like some of the new SystemVerilog enhancements.