Author Topic: SystemVerilog Beautification Issues  (Read 1769 times)

warnerrs

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SystemVerilog Beautification Issues
« on: February 29, 2016, 11:19:59 pm »
Here's one I just bumped into. The beautifier doesn't understand "extern", and indents subsequent lines.

Code: [Select]
    extern function new(string name, uvm_component parent);
        extern virtual function void build_phase(uvm_phase phase);
            extern virtual task run_phase(uvm_phase phase);
                extern virtual task do_addr_phase();
                    extern virtual task do_data_phase();

patrick

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Re: SystemVerilog Beautification Issues
« Reply #1 on: March 01, 2016, 02:45:09 pm »
I can reproduce that, definitely a bug.  I don't see a way to work around it.  It's not hot-fixable either, so my fix for this will be in the next release.

warnerrs

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Re: SystemVerilog Beautification Issues
« Reply #2 on: March 08, 2016, 05:11:19 pm »
Here's some more reference code that should help with testing SystemVerilog beautification and auto-indenting.
Code: [Select]
class Env extends uvm_env;

    virtual clock_vif sys_pc_clk,
                                        block_clk;

    virtual discrete_vif sys_pc_rst_n,
                   block_rst_n;

  AhbMasterAgent ahb;

  `uvm_component_utils( Env )

    function new( string name, uvm_component parent );
        super.new( name, parent );
    endfunction

    function void build_phase( uvm_phase phase );
    ClockPkg::get_vif(       this, "", "sys_pc_clk", sys_pc_clk );
    ClockPkg::get_vif(       this, "", "block_clk", block_clk );

    DiscretePkg::get_vif(       this, "", "sys_pc_rst_n", sys_pc_rst_n );
    DiscretePkg::get_vif(       this, "", "block_rst_n", block_rst_n );
    endfunction

function void end_of_elaboration_phase( uvm_phase phase );
                                        `uvm_info( "PROGRESS", $sformatf("Reached %m"), UVM_LOW )
endfunction

endclass

I also have a video showing the undesirable behavior: https://youtu.be/c6eu29KxG4Y

patrick

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Re: SystemVerilog Beautification Issues
« Reply #3 on: March 08, 2016, 05:53:58 pm »
Nice, thanks for recording the video, that makes it clear.  In addition to the bad indents for the declarations, it seems there's still something not right with the indents on macro calls.

patrick

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Re: SystemVerilog Beautification Issues
« Reply #4 on: April 14, 2016, 04:48:42 pm »
20.0.2 just came out, and it has the following changes for SystemVerilog:

 The virtual interface declarations have their names aligned when "Align Variables" is enabled.  If it's not enabled, they just get a continuation indent.  Also fixed a couple of problems with var alignment for members of classes I noticed in passing.

I also put in fixes for the problems of macro functions ending up with the wrong indent relative to the surrounding code, so "`uvm_component_utils( Env )" won't be hanging out in its own column anymore.