20.0.2 just came out, and it has the following changes for SystemVerilog:
The virtual interface declarations have their names aligned when "Align Variables" is enabled. If it's not enabled, they just get a continuation indent. Also fixed a couple of problems with var alignment for members of classes I noticed in passing.
I also put in fixes for the problems of macro functions ending up with the wrong indent relative to the surrounding code, so "`uvm_component_utils( Env )" won't be hanging out in its own column anymore.