Author Topic: System Verilog Property causes SE to hang  (Read 1768 times)

pmsteinm

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System Verilog Property causes SE to hang
« on: April 01, 2016, 03:58:27 pm »
I have attached a module with a System Verilog property comment out. If you remove the comment you should see Slickedit start using 100% cpu and stop responding. The way found this was I had an SV file as part of a project with this construct add to it in a newer version. When I had clearcase update my files to this new version I noticed slickedit started using 150% cpu (on a 2 CPU machine). It did this over the weekend without my realizing it. I eventually traced the problem to this file being in the project. When I removed it and killed and restarted slickedit the CPU usage went back to almost 0. When I try to open this file directly slickedit hangs. I narrowed down the specific problem in the file to the property I have added to the attached test file. In the test file nothing is defined or declared but that didn't make a different in the real file. Besides slickedit shouldn't hang while implementing incomplete code.

My system info (hotfix 7 is applied):
lickEdit Pro 2015 (v20.0.1.3 64-bit)

Build Date: March 23, 2016
Emulation: CUA

OS: Linux
OS Version: SUSE Linux Enterprise Desktop 11 (x86_64)
Kernel Level: 3.0.101-0.47.55-default
Build Version: #1 SMP Thu May 28 08:25:11 UTC 2015 (dc083ee)
Processor Architecture: x86_64

X Server Vendor: The X.Org Foundation
Memory: 91% Load, 11997MB/13110MB Virtual
Shell Information: /bin/tcsh
Screen Size: 5754 x 1142
« Last Edit: April 01, 2016, 04:07:35 pm by pmsteinm »

patrick

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Re: System Verilog Property causes SE to hang
« Reply #1 on: April 01, 2016, 04:35:55 pm »
I can reproduce that.  Looks like a parser bug, the error handling has a bug and is getting stuck.  I'll take a look at it.  Thanks for the report.

patrick

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Re: System Verilog Property causes SE to hang
« Reply #2 on: April 07, 2016, 02:32:21 pm »
This is fixed for the upcoming v20.0.2 release.