If I use the interface in module's port list, the beautify of system seem can't recognize the interface and alignment seems not right.
The code above is my example.
Before:
interface fifo_if #(parameter DW = 32, FIFO_AW = 32);
logic valid;
logic ready;
logic [DW-1:0] dat;
modport fifoOutput(
// data port
output valid,
output dat,
input ready
);
modport fifoInput(
// data port
input valid,
input dat,
output ready
);
endinterface : fifo_if
module testModule(
input clk,
input rstn,
fifo_if.fifoInput fifoInfIn,
fifo_if.fifoOutput fifoInfOut,
input datIn
);
endmodule
After beautify of system verilog
interface fifo_if #(parameter DW = 32, FIFO_AW = 32);
logic valid;
logic ready;
logic [DW-1:0] dat;
modport fifoOutput(
// data port
output valid,
output dat,
input ready
);
modport fifoInput(
// data port
input valid,
input dat,
output ready
);
endinterface : fifo_if
module testModule(
input clk,
input rstn,
fifo_if.fifoInput fifoInfIn,
fifo_if.fifoOutput fifoInfOut,
input datIn
);
endmodule