Author Topic: One question about system verilog beautify  (Read 1831 times)

ycyang

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One question about system verilog beautify
« on: May 30, 2016, 04:00:50 pm »
If I use the interface in module's port list, the beautify of system seem can't recognize the interface and alignment seems not right.
The code above is my example.
Before:
interface fifo_if #(parameter DW = 32, FIFO_AW = 32);
    logic          valid;
    logic          ready;
    logic [DW-1:0] dat;
    modport fifoOutput(
        // data port
        output valid,
        output dat,
        input ready
        );

    modport fifoInput(
        // data port
        input valid,
        input dat,
        output ready
        );
endinterface : fifo_if

module testModule(
    input clk,
    input rstn,
    fifo_if.fifoInput fifoInfIn,
    fifo_if.fifoOutput fifoInfOut,
    input datIn
);
endmodule

After beautify of system verilog
interface fifo_if #(parameter DW = 32, FIFO_AW = 32);

    logic          valid;
    logic          ready;
    logic [DW-1:0] dat;

    modport fifoOutput(
        // data port
        output valid,
        output dat,
        input ready
        );

    modport fifoInput(
        // data port
        input valid,
        input dat,
        output ready
        );

endinterface : fifo_if


module testModule(
    input clk,
    input rstn,

          fifo_if.fifoInput fifoInfIn,
          fifo_if.fifoOutput fifoInfOut,

    input datIn

);
endmodule



patrick

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Re: One question about system verilog beautify
« Reply #1 on: June 01, 2016, 01:43:31 pm »
I can reproduce that, I'll take a look at it.  Thanks for letting us know.

patrick

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Re: One question about system verilog beautify
« Reply #2 on: August 01, 2016, 07:19:21 pm »
I've checked in a fix for this for the next beta build of v21.