There is a feature for C/C++ under Tools -> Options -> Languages -> Application Languages -> C/C++ -> C/C++ Preprocessing that let's you define macros that you want Slick to understand.
I don't see an equivalent feature listed under: Tools -> Options -> Languages -> Hardware Description Languages -> SystemVerilog or Verilog
The UVM methodology defines a lot of symbols hidden inside it's macros. Is there any hidden facility that can enable this same feature for SystemVerilog, just like in C/C++?
-Ryan