Author Topic: Verilog Preprocessing?  (Read 2851 times)

warnerrs

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Verilog Preprocessing?
« on: June 24, 2013, 05:09:25 PM »
There is a feature for C/C++ under Tools -> Options -> Languages -> Application Languages -> C/C++ -> C/C++ Preprocessing that let's you define macros that you want Slick to understand.

I don't see an equivalent feature listed under: Tools -> Options -> Languages -> Hardware Description Languages -> SystemVerilog or Verilog

The UVM methodology defines a lot of symbols hidden inside it's macros.  Is there any hidden facility that can enable this same feature for SystemVerilog, just like in C/C++?

-Ryan

Dennis

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Re: Verilog Preprocessing?
« Reply #1 on: August 19, 2016, 06:13:02 PM »
Just an FYI on this topic, we are working on this for SlickEdit 2016.  We are hoping to get the first implementation into beta4.