Author Topic: Verilog 2001 support/improvements  (Read 592 times)

bonito

  • Community Member
  • Posts: 8
  • Hero Points: 1
Verilog 2001 support/improvements
« on: September 15, 2010, 02:49:51 am »
since verilog 2001 is more and more popular than verilg, so if the next version of slickedit could support verilog 2001 would be a great thing. :)

Lee

  • SlickEdit Team Member
  • Senior Community Member
  • *
  • Posts: 1299
  • Hero Points: 130
Re: Verilog 2001 support/improvements
« Reply #1 on: September 15, 2010, 01:04:32 pm »
@bonito: SlickEdit's Verilog support was updated with the 2009 (15.0.1) release to support the 2005 language spec (IEEE Std 1364-2005).

bonito

  • Community Member
  • Posts: 8
  • Hero Points: 1
Re: Verilog 2001 support/improvements
« Reply #2 on: September 30, 2010, 07:45:54 am »
@bonito: SlickEdit's Verilog support was updated with the 2009 (15.0.1) release to support the 2005 language spec (IEEE Std 1364-2005).

@Lee: But I find that "localparam" is still not a keywords in 15.0.1, which is introduced in verilog 2001. And Slickedit 15.0.1 still can not recognize the "wire" variable which is defined directly by such a style "assign a = b & c;" (verilog 2001 allows to omit the variable definition "wire a;" ).