Author Topic: SystemVerilog / Verilog preprocessing  (Read 1555 times)

warnerrs

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SystemVerilog / Verilog preprocessing
« on: June 24, 2013, 02:13:00 pm »
Since Slick does not process include statements, it does not handle the way SystemVerilog users define packages (namespaces). The only mechanism SystemVerilog provides for using multiple files to comprise a package is for the package to `include other files.

A hopefully simple to implement workaround to this issue would be to add a pragma that the tagger recognizes.  That pragma would tell the tagger all the symbols found in the current file belong to a specific package.  There should be no performance issues with this approach.

Regards,
-Ryan

warnerrs

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Re: SystemVerilog / Verilog preprocessing
« Reply #1 on: June 17, 2014, 03:13:27 pm »
I'm waiting on SystemVerilog bug fixes. Hoping 2014 beta comes out soon!

warnerrs

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Re: SystemVerilog / Verilog preprocessing
« Reply #2 on: June 27, 2014, 06:22:19 pm »
Clark,

I tried replying to your message, but I keep getting "User 'Clark' has blocked your personal message.". So I'm posting my reply here.

Re: SystemVerilog

How about a custom javadoc tag?  Something akin to Doxygen's \ingroup tag.

/**
 * @inpackage <package_name>
 */

This shall support being parsed before or after the file containing the actual package definition. It shall affect the scope of the parsing from the point it is encountered until the end of the file, but not affect any files parsed after that.  It shall support multiple files having the same statement, it just means all of those files are added to the same package.

Maybe the tag should be called @vs.inpackage to make it clear it is a SlickEdit specific tag, although I'm not too worried about that.

Thanks,
Ryan

I noticed you had a suggestion for using a pragma to specify a package for a file that our tagging engine could understand. I assume the compiler doesn't already have a pragma for this because it wouldn't need it. If we defined our own pragma, would this cause a compiler error? If this doesn't cause a compiler, what syntax would you suggest?

Thanks for all your suggestions. I noticed that you have a number of good ones.

Thanks
Clark

Clark

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Re: SystemVerilog / Verilog preprocessing
« Reply #3 on: June 27, 2014, 06:29:12 pm »
Hmm...not sure why it's blocked. I'll look into it.

I suspect our verilog lexer removes comments so the parsing code doesn't have to constantly skip/check the comment token. It's possible just a bit messy. Is there any preprocessing syntax which would work (i.e. "`prama package(<package_name>")?

warnerrs

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Re: SystemVerilog / Verilog preprocessing
« Reply #4 on: June 27, 2014, 08:16:37 pm »
The typical user defined pragma in verilog is done in a comment
  \\ pragma

I suppose we could define an empty macro:
  `define inpackage(x)
And then use that like:
  `inpackage(FooPkg)

The only thing I don't like about that, is you have to do that `define somewhere. Doing it in the file is less than ideal, and doing it outside the file creates compile dependencies.

I also tested a user defined attribute, and got this to work:

Code: [Select]
class A;
   int x;
endclass // A

(* inpackage="FooPkg" *) class B extends A;
   int y;
endclass // B

// this class is not in FooPkg
class C extends A;
   int z;
endclass // C

module m;
   initial begin
      A a;
      B b = new;
      C c;

      a = b;
      $cast(c,a);

      $display("\n\n\n ------ got here? -------\n\n\n");
   end
endmodule // m

There are some rules to attributes though. The attribute name can't be a keyword, so I used 'inpackage' instead of 'package'. The attribute value must be a valid verilog data type, so I had to use a quoted string.

The LRM also state's that the attribute only applies to entity immediately following it. So in this example, class B has the inpackage=FooPkg attribute, but the other classes do not.

-Ryan

Clark

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Re: SystemVerilog / Verilog preprocessing
« Reply #5 on: June 27, 2014, 08:27:48 pm »
I'll try to make a comment work. I prefer a line comment since its less to type or parse.

warnerrs

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Re: SystemVerilog / Verilog preprocessing
« Reply #6 on: September 05, 2014, 08:13:16 pm »
I'll try to make a comment work. I prefer a line comment since its less to type or parse.

Has work related to this made it into the beta? I didn't see anything in the release notes, but thought I'd ask.

The SV tagger is working with classes in packages now, so that's a major improvement.

-Ryan

warnerrs

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Re: SystemVerilog / Verilog preprocessing
« Reply #7 on: September 08, 2014, 04:59:08 am »
There isn't a Verilog or SystemVerilog Preprocessor configuration like there is for C/C++. The UVM library uses macros to generate code that I'd like the tagger to see and understand.  Maybe there's a way to accomplish this with a SlickEdit macro in the mean time?

-Ryan

warnerrs

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Re: SystemVerilog / Verilog preprocessing
« Reply #8 on: March 21, 2016, 12:12:08 am »
Any chance we'll be getting SystemVerilog Preprocessing soon, same as C/C++ Preprocessing?

The tagger is missing an awful lot of symbols generated by UVM macros.

warnerrs

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Re: SystemVerilog / Verilog preprocessing
« Reply #9 on: April 07, 2016, 08:21:37 pm »
Clark,

This is a very old thread. I haven't heard that anything came of it, did it ever go anywhere?

Clark,

I tried replying to your message, but I keep getting "User 'Clark' has blocked your personal message.". So I'm posting my reply here.

Re: SystemVerilog

How about a custom javadoc tag?  Something akin to Doxygen's \ingroup tag.

/**
 * @inpackage <package_name>
 */

This shall support being parsed before or after the file containing the actual package definition. It shall affect the scope of the parsing from the point it is encountered until the end of the file, but not affect any files parsed after that.  It shall support multiple files having the same statement, it just means all of those files are added to the same package.

Maybe the tag should be called @vs.inpackage to make it clear it is a SlickEdit specific tag, although I'm not too worried about that.

Thanks,
Ryan

I noticed you had a suggestion for using a pragma to specify a package for a file that our tagging engine could understand. I assume the compiler doesn't already have a pragma for this because it wouldn't need it. If we defined our own pragma, would this cause a compiler error? If this doesn't cause a compiler, what syntax would you suggest?

Thanks for all your suggestions. I noticed that you have a number of good ones.

Thanks
Clark

Dennis

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Re: SystemVerilog / Verilog preprocessing
« Reply #10 on: November 04, 2016, 09:19:59 pm »
FWIW:  SlickEdit 2016 has Verilog and SystemVerilog preprocessing support.

warnerrs

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Re: SystemVerilog / Verilog preprocessing
« Reply #11 on: November 16, 2016, 07:58:18 am »
I was looking through the release notes looking for this, but it wasn't listed.  Thanks for the reply, it's worth a lot!

I've changed jobs, and lost access to my previous license. I currently have access to an Eclipse based tool which does parse macros. For UVM testbenches, this a "killer feature", so while I've been missing the ease with which I performed editing in SE, I've been living with eclipse specifically for this feature.

Time for a trial eval. Thanks!

Dennis

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Re: SystemVerilog / Verilog preprocessing
« Reply #12 on: November 17, 2016, 03:13:00 pm »
Hmm, yeah, it made it into the readme (look at the release notes on the Help > About dialog), but did not make it into the docs.