Beautifier, Verilog module instantiation alignment issue with defines

[ehoffman]

There is issue beautifying Verilog module instantiation when you are using a define, as demonstrated bellow:

Before beautify:

Code: [Select]

    `define WIDTH 32

    module_a instance_a(
      .a_port(17),
         .another_port      (32'b0),
       .yet_another_port (a_wire)
           );

    module_a instance_b(
      .a_port (17),
         .another_port (`WIDTH'b0),
       .yet_another_port(a_wire)
           );

After Beautify:

Code: [Select]

    `define WIDTH 32

    module_a instance_a(
                        .a_port           (17),
                        .another_port     (32'b0),
                        .yet_another_port (a_wire)
    );

    module_a instance_b(
                        .a_port (17),
                        .another_port (`WIDTH'b0),
                        .yet_another_port(a_wire)
                       );

You see, the second instance does not align the parameters.  This is because the beautifier get confused by the `WIDTH'b0

This is with SlickEdit v21.0.0.12


Also, a second issue, the 'after beautifier' above was obtained by beautifying the whole buffer.  If you select a block instead, and beautify just that block (that is, the example above is part of a larger file, and you select just the instances shown above, and beautify this block), you get:

Selection beautify:

Code: [Select]

    `define WIDTH 32

    module_a instance_a(
                        .a_port(17),
                        .another_port      (32'h0),
                        .yet_another_port (a_wire)
                        );

    module_a instance_b(
                        .a_port (17),
                        .another_port (`WIDTH'h0),
                        .yet_another_port(a_wire)
                        );

So, the parameters are not aligned.

Regards,
Eric

[patrick]

I need to get your beautifier profile, I'm not quite seeing this with the default profile or by making obvious changes.  If you have v21, you can attach the user.cfg.xml that's in your configuration directory file to your reply.  For <= v20, attach the vusr_beautifier.xml that's in your configuration directory.

Thanks for the report.

[ehoffman]

Hello, thanks.  Actually, this is v21, but SE seem to still be using user.cfg.xml.

The beautifier setting for Verilog is

Code: [Select]

<language.verilog.beautifier_profiles n="language.verilog.beautifier_profiles.My Default" version="1">
<p n="align_assignments" v="1"/>
<p n="align_module_instantiations" v="1"/>
<p n="align_module_parameters" v="1"/>
<p n="align_on_assignment_op" v="1"/>
<p n="align_trinary_branches" v="0"/>
<p n="bl_after_end_block_for" v="0" apply="0"/>
<p n="bl_after_end_block_if" v="0" apply="0"/>
<p n="bl_after_end_block_while" v="0" apply="0"/>
<p n="bl_after_start_block_for" v="0" apply="0"/>
<p n="bl_after_start_block_if" v="0" apply="1"/>
<p n="bl_after_start_block_while" v="0" apply="0"/>
<p n="braceloc_for" v="1"/>
<p n="braceloc_if" v="1"/>
<p n="braceloc_multiline_cond" v="10"/>
<p n="braceloc_while" v="1"/>
<p n="indent_col1_comments" v="1"/>
<p n="indent_comments" v="1"/>
<p n="indent_if_of_else_if" v="1" apply="1"/>
<p n="indent_label" v="1"/>
<p n="indent_width_continuation" v="4"/>
<p n="indent_width_label" v="4"/>
<p n="indent_with_tabs" v="0"/>
<p n="leave_multiple_stmt" v="1"/>
<p n="listalign2_expr_parens" v="0"/>
<p n="listalign_fun_call_params" v="0"/>
<p n="max_line_len" v="80" apply="0"/>
<p n="nl_before_else" v="1" apply="1"/>
<p n="nl_empty_block" v="0" apply="1"/>
<p n="oneline_elseif" v="1" apply="1"/>
<p n="oneline_unblocked_else" v="0" apply="1"/>
<p n="oneline_unblocked_statement" v="0" apply="1"/>
<p n="oneline_unblocked_then" v="0" apply="1"/>
<p n="original_tab_size" v="8" apply="1"/>
<p n="require_new_line_after_var_decl_comma" v="0"/>
<p n="require_new_line_at_eof" v="1"/>
<p n="rm_dup_spaces" v="0"/>
<p n="rm_trailing_spaces" v="1"/>
<p n="sp_array_decl_before_lbracket" v="0" apply="1"/>
<p n="sp_expr_after_rparen" v="0" apply="1"/>
<p n="sp_expr_before_lparen" v="0" apply="1"/>
<p n="sp_for_before_lparen" v="1" apply="1"/>
<p n="sp_fun_call_before_lparen" v="0" apply="1"/>
<p n="sp_fun_call_empty_parens" v="0" apply="1"/>
<p n="sp_if_before_lparen" v="1" apply="1"/>
<p n="sp_stmt_after_semicolon" v="1" apply="1"/>
<p n="sp_stmt_before_semicolon" v="0" apply="1"/>
<p n="sp_while_after_rparen" v="1" apply="1"/>
<p n="sp_while_before_lparen" v="1" apply="1"/>
<p n="sppad_array_decl_brackets" v="0" apply="1"/>
<p n="sppad_expr_parens" v="0" apply="1"/>
<p n="sppad_for_parens" v="0" apply="1"/>
<p n="sppad_fun_call_parens" v="0" apply="1"/>
<p n="sppad_if_parens" v="0" apply="1"/>
<p n="sppad_while_parens" v="0" apply="1"/>
<p n="spstyle_for_comma" v="2" apply="1"/>
<p n="spstyle_for_semicolon" v="2" apply="1"/>
<p n="spstyle_fun_call_comma" v="2" apply="1"/>
<p n="spstyle_op_assignment" v="3" apply="1"/>
<p n="spstyle_op_binary" v="3" apply="1"/>
<p n="spstyle_op_bitwise" v="3" apply="1"/>
<p n="spstyle_op_comparison" v="3" apply="1"/>
<p n="spstyle_op_logical" v="3" apply="1"/>
<p n="spstyle_op_mult" v="3" apply="1"/>
<p n="spstyle_op_unary" v="0" apply="1"/>
<p n="syntax_indent" v="4"/>
<p n="tab_size" v="8"/>
<p n="trailing_comment_col" v="70"/>
<p n="trailing_comment_style" v="2"/>
</language.verilog.beautifier_profiles>

Regards,
Eric

[patrick]

Ok, I can see it now.  Part of my initial problem was not putting your snippet in a valid module.  I have an idea of what's going wrong here.

I'll look at the selection formatting too - I got a defect for something similar in SystemVerilog last week, so I've already done some work on sorting that out.