I'm defining preprocessor macros to be expanded under SystemVerilog options. The tagger sees the expanded code, but is there some way to preview the expansion in the editor? Selective Display's "Preprocessor directives" option is greyed out for SystemVerilog, but even when I played around with that in C++ it only seems to support hiding #if/else branches.
And while a selective display like expansion would be best, even a command that would just do the expansion in the buffer would be acceptable. I can always revert it later.