Hi,
Great progress on the beautification of SystemVerilog in the last couple of versions.
I did just run into an issue when working with interfaces. WHen an interface is declared in the module port definition, beautify breaks, and differently depending on where in the port list the interface is. Snippet below.
It seems happiest when the interfaces are listed first, but my sample size is small. Is there a setting I'm missing in the beautify configuration?
-Tim.
//original
module testModule
(
input logic inputA,
input logic inputB,
interface interfaceA,
output logic [2:0] outputA,
interface interfaceB,
output logic [7:0] outputB,
interface interfaceC
);
endmodule
//beautified
module testModule
(
input logic inputA,
input logic inputB,
interface interfaceA,
output logic [2:0] outputA,
interface interfaceB,
output logic [7:0] outputB,
interface interfaceC
);
endmodule
//original
module testModule
(
input logic inputA,
input logic inputB,
output logic [2:0] outputA,
output logic [7:0] outputB,
interface interfaceB,
interface interfaceA,
interface interfaceC
);
endmodule
//beautified
module testModule
(
input logic inputA,
input logic inputB,
output logic [2:0] outputA,
output logic [7:0] outputB,
interface interfaceB,
interface interfaceA,
interface interfaceC
);
endmodule
//original
module testModule
(
interface interfaceB,
interface interfaceA,
interface interfaceC,
input logic inputA,
input logic inputB,
output logic [2:0] outputA,
output logic [7:0] outputB
);
endmodule
//beautified
module testModule
(
interface interfaceB,
interface interfaceA,
interface interfaceC,
input logic inputA,
input logic inputB,
output logic [2:0] outputA,
output logic [7:0] outputB
);
endmodule