systemVerilog beautify doesn't handle interfaces in module declaration

[tim_k]

Hi,

Great progress on the beautification of SystemVerilog in the last couple of versions.
I did just run into an issue when working with interfaces. WHen an interface is declared in the module port definition, beautify breaks, and differently depending on where in the port list the interface is. Snippet below.

It seems happiest when the interfaces are listed first, but my sample size is small. Is there a setting I'm missing in the beautify configuration?

-Tim.

Code: [Select]

//original
module testModule
  (
    input logic inputA,
    input logic inputB,
    interface   interfaceA,
    output logic [2:0] outputA,
    interface interfaceB,
    output logic [7:0] outputB,
    interface interfaceC
    );
endmodule

//beautified
module testModule
(
 input logic  inputA,
 input logic  inputB,
 interface   interfaceA,
 output logic [2:0] outputA,
 interface interfaceB,
 output logic [7:0] outputB,
 interface interfaceC
);
endmodule

//original
module testModule
  (
    input logic inputA,
    input logic inputB,
    output logic [2:0] outputA,
    output logic [7:0] outputB,
      interface interfaceB,
      interface   interfaceA,
        interface interfaceC
    );
endmodule

//beautified
module testModule
(
 input logic        inputA,
 input logic        inputB,
 output logic [2:0] outputA,
 output logic [7:0] outputB,
 interface interfaceB,
                    interface   interfaceA,
                    interface interfaceC
);
endmodule

//original
module testModule
  (
    interface interfaceB,
                       interface   interfaceA,
                       interface interfaceC,
                         input logic        inputA,
    input logic        inputB,
    output logic [2:0] outputA,
    output logic [7:0] outputB
    );
endmodule

//beautified
module testModule
(
 interface interfaceB,
 interface   interfaceA,
 interface interfaceC,
 input logic        inputA,
 input logic        inputB,
 output logic [2:0] outputA,
 output logic [7:0] outputB
);
endmodule




[patrick]

No, that looks like a bug, though I'm not sure why it's doing that yet.  I'll take a look at it, thanks for the report.

[tim_k]

If there's a way to dump the beautify settings, I'll forward that to you. I've got some modifications from the default. Although the default doesn't do much better.

-Tim

[patrick]

You can grab the user.cfg.xml file from your configuration directory, and either post on PM that.  It contains all of the settings that are different from the defaults.

[tim_k]

Here's the relevant portion of my user.cfg.xml:

Code: [Select]

<language.systemverilog.beautifier_profiles n="language.systemverilog.beautifier_profiles.My Defaults" version="1">
<align_assignments v="1"/>
<align_module_instantiations v="1"/>
<align_module_parameters v="1"/>
<align_on_assignment_op v="1"/>
<align_trinary_branches v="1"/>
<bl_after_end_block_for v="0" apply="0"/>
<bl_after_end_block_if v="0" apply="0"/>
<bl_after_end_block_while v="0" apply="0"/>
<bl_after_start_block_for v="0" apply="0"/>
<bl_after_start_block_if v="1" apply="0"/>
<bl_after_start_block_while v="0" apply="0"/>
<braceloc_for v="0"/>
<braceloc_if v="0"/>
<braceloc_multiline_cond v="10"/>
<braceloc_while v="0"/>
<indent_col1_comments v="1"/>
<indent_comments v="1"/>
<indent_if_of_else_if v="1" apply="1"/>
<indent_label v="0"/>
<indent_width_continuation v="2"/>
<indent_width_label v="1"/>
<indent_with_tabs v="0"/>
<justify_var_decl_name v="0" apply="1"/>
<leave_multiple_stmt v="1"/>
<listalign2_expr_parens v="0"/>
<listalign_fun_call_params v="2"/>
<max_line_len v="80" apply="0"/>
<nl_before_else v="0" apply="1"/>
<nl_empty_block v="1" apply="1"/>
<oneline_elseif v="1" apply="1"/>
<oneline_unblocked_else v="0" apply="1"/>
<oneline_unblocked_statement v="0" apply="0"/>
<oneline_unblocked_then v="0" apply="1"/>
<original_tab_size v="2" apply="1"/>
<require_new_line_after_var_decl_comma v="1"/>
<require_new_line_at_eof v="1"/>
<rm_dup_spaces v="0"/>
<rm_trailing_spaces v="1"/>
<sp_array_decl_before_lbracket v="0" apply="1"/>
<sp_expr_after_rparen v="0" apply="1"/>
<sp_expr_before_lparen v="0" apply="1"/>
<sp_for_before_lparen v="1" apply="1"/>
<sp_fun_call_before_lparen v="0" apply="1"/>
<sp_fun_call_empty_parens v="0" apply="1"/>
<sp_if_before_lparen v="1" apply="1"/>
<sp_stmt_after_semicolon v="1" apply="1"/>
<sp_stmt_before_semicolon v="0" apply="1"/>
<sp_while_after_rparen v="1" apply="1"/>
<sp_while_before_lparen v="1" apply="1"/>
<sppad_array_decl_brackets v="0" apply="1"/>
<sppad_expr_parens v="0" apply="1"/>
<sppad_for_parens v="0" apply="1"/>
<sppad_fun_call_parens v="0" apply="1"/>
<sppad_if_parens v="0" apply="1"/>
<sppad_while_parens v="0" apply="1"/>
<spstyle_for_comma v="2" apply="1"/>
<spstyle_for_semicolon v="2" apply="1"/>
<spstyle_fun_call_comma v="2" apply="1"/>
<spstyle_op_assignment v="3" apply="1"/>
<spstyle_op_binary v="3" apply="1"/>
<spstyle_op_bitwise v="3" apply="1"/>
<spstyle_op_comparison v="3" apply="1"/>
<spstyle_op_logical v="3" apply="1"/>
<spstyle_op_mult v="3" apply="1"/>
<spstyle_op_unary v="0" apply="1"/>
<syntax_indent v="2"/>
<tab_size v="2"/>
<trailing_comment_col v="70"/>
<trailing_comment_style v="1"/>
</language.systemverilog.beautifier_profiles>