Author Topic: Verilog: How to instantiate module  (Read 1260 times)

whyphy

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Verilog: How to instantiate module
« on: October 15, 2019, 02:27:04 pm »
Does SlickEdit have a function that will instantiate a module in Verilog (or SystemVerilog)?

I cannot find any documentation on how to do so, but it seems like this would be part of a Verilog IDE.


patrick

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Re: Verilog: How to instantiate module
« Reply #1 on: October 15, 2019, 03:54:23 pm »
No, there currently isn't a command that can instantiate a module.