strong behavior about system verilog beautify

[ycyang]

I use system verilog beautify recently, but I got the strong result. Any one had some issue?

Original code :
module test_case();
    logic [7:0] slave_cmd_reg;
    logic [7:0] slave_rdata_low_reg;
    logic [7:0] slave_rdata_high_reg;

    task automatic assign_0x4c_reg();
        case (slave_cmd_reg)
            8'h00:
                {slave_rdata_low_reg} <= 'd0;
            8'h01:
                {slave_rdata_high_reg, slave_rdata_low_reg} <= 'd0;
            default:
                {slave_rdata_low_reg} <= 8'h0;
        endcase
    endtask
endmodule

After beautify:
module test_case();
    logic [7:0] slave_cmd_reg;
    logic [7:0] slave_rdata_low_reg;
    logic [7:0] slave_rdata_high_reg;

    task automatic assign_0x4c_reg();
        case (slave_cmd_reg)
            8'h00:
                {slave_rdata_low_reg} <= 'd0;
                8'h01:
                {slave_rdata_high_reg, slave_rdata_low_reg} <= 'd0;
                default:
                {slave_rdata_low_reg} <= 8'h0;
                endcase
        endtask
        endmodule

[patrick]

I can reproduce it, and it looks like it may be a parsing error in the beautifier.  I'll take a look at it.  I suspect this won't be hot-fixable, but would need to be fixed for the next point or major release.

[ycyang]

thank you for the update.

[patrick]

This was not hot-fixable.  The fix will be in the upcoming beta 2 for SlickEdit 2020 v25.