SE can not recognize "define" in verilog, a BUG?

[bonito]

I found that SE can not recognize the "`define" grammar in verilog such as the "CLK" in attachment. Is this a bug?

Software version information is bellow:

SlickEdit 2011 (v16.0.3.0 32-bit)
Build Date: October 06, 2011
Emulation: CUA
OS: Windows XP
OS Version: 5.01.2600  Service Pack 3
Project Type: Verilog: Model Technology ModelSim
Language: .v (Verilog)
Hotfixes: (Revision: 10)

[Lee]

That would be a bug.  I will file a defect and see if it can be hotfixed or fixed in the next release.

[bonito]

I find another bug of Slickedit with verilog, that it can not recognize the defined symbol after XOR "^" such as the attachment.

Wish these bugs can be fixed!

[Lee]

Thanks for the defect report.  Both items in this thread will be fixed in the next SlickEdit release.