Author Topic: [Bug] Something wrong with include in verilog !  (Read 2262 times)


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[Bug] Something wrong with include in verilog !
« on: August 30, 2012, 10:18:53 am »
SlickEdit 2012 (v17.0.2.0 32-bit)
I found that if did not comment out something like "`include "define.v" " Slickedit will make wrong with the reorganization of some defined symbols.
I think it should be a bug. All the lines in "define.v" are something like "`define REG_MAILBOX 4'b0000", and it is OK to be compiled with verilog.


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Re: [Bug] Something wrong with include in verilog !
« Reply #1 on: August 30, 2012, 01:47:16 pm »
Thanks for the report.  Does appear to be an issue with parsing preprocessing directive statements in Verilog.  This is not hotfixable so it will have to be addressed in the next release.  If you are on the Windows build, contact Customer support and refer them to this forum post.  We should be able to get you an updated parser dll that addresses this in the meantime.