Thanks all for your feedback. I'm using SlickEdit 16.0.3, and my .v files are recognized as Verilog no problem. Syntax highlighting and Defs work. Not using any macros.
So I tried for the n'th time going through all the Defs possibilities (any way to toggle many at a time btw vs right-click/select each one?), and noticed the instantiations actually *were* there (Variables->Data Members -- my apologies), but unfortunately lost in the sea of "wire" and "reg" declarations. It's unfortunate that 2 fundamentally different object types get amalgamated this way. This is a general problem btw with the Slick Defs categories vs HDLs in general: the hard-coded software-oriented Defs categories don't map so well for HDLs.
Is there any way to "re-categorize" things in Def categories ?
Lastly, can Slick identify Verilog "always" blocks? In Slick's VHDL, every "process" has a label and thus come up neatly in the Defs window which makes it really easy to navigate through source code. Not so much in Verilog, so far as I can tell...?
Thanks in advance for any feedback and tips, I love slick for VHDL, tcl, C, and would love to keep using it for Verilog!