Author Topic: Verilog tagger not respecting `includes  (Read 1809 times)

warnerrs

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Verilog tagger not respecting `includes
« on: June 13, 2013, 02:45:03 pm »
Take these two files.

--- pkg.sv ---
Code: [Select]
package pkg;

    class foo;
        int x;
    endclass

`include "bar.sv"

endpackage

--- bar.sv ---
Code: [Select]
class bar;
    int y;
endclass

The tagger does not correctly locate class bar inside of the package pkg.  It puts it in the global space instead. I've attached my small example.  Anyone have this working?

warnerrs

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Re: Verilog tagger not respecting `includes
« Reply #1 on: July 02, 2013, 04:55:59 pm »
I've come up with a workaround.  Although it doesn't work with code that I do not own, such as the UVM library.  I wrap my package included source files with:

Code: [Select]
`ifdef SLICKEDIT
package <packagename>;
`endif

// original file

`ifdef SLICKEDIT
endpackage
`endif

Still not as nice as a one liner pragma added at the beginning of the file.

-Ryan

Dennis

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Re: Verilog tagger not respecting `includes
« Reply #2 on: August 19, 2016, 06:16:48 pm »
Just an FYI on this topic, we are working on this for SlickEdit 2016.  We are hoping to get the first implementation into beta4.