SlickEdit Community

Archived Read Only Forums => SlickEdit 2015 v20 Beta Discussion => Topic started by: warnerrs on September 23, 2015, 07:13:13 pm

Title: SystemVerilog interface beautification
Post by: warnerrs on September 23, 2015, 07:13:13 pm
Code inside SystemVerilog interfaces does not beautify.

Code: [Select]
interface irq_if;
logic irq_n;
task test;
endtask
modport master(output irq_n);
modport slave(input irq_n);
endinterface
Title: Re: SystemVerilog interface beautification
Post by: warnerrs on September 23, 2015, 07:18:34 pm
Packages have the same problem.

Code: [Select]
package Vip;
integer x;
class UseRif;
    virtual reg_if rif;
endclass
endpackage
Title: Re: SystemVerilog interface beautification
Post by: patrick on September 23, 2015, 07:24:00 pm
I'm taking a look at it, thanks for the report.
Title: Re: SystemVerilog interface beautification
Post by: patrick on September 23, 2015, 08:09:27 pm
Fixed for the next release.  It looks like I made the same mistake for 'primitive' declarations as well, so I'll fix that for the next release as well.