SlickEdit Community
Archived Beta Discussions => SlickEdit 201x Beta Discussions => SlickEdit 2015 v20 Beta Discussion => Topic started by: warnerrs on September 23, 2015, 07:13:13 PM
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Code inside SystemVerilog interfaces does not beautify.
interface irq_if;
logic irq_n;
task test;
endtask
modport master(output irq_n);
modport slave(input irq_n);
endinterface
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Packages have the same problem.
package Vip;
integer x;
class UseRif;
virtual reg_if rif;
endclass
endpackage
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I'm taking a look at it, thanks for the report.
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Fixed for the next release. It looks like I made the same mistake for 'primitive' declarations as well, so I'll fix that for the next release as well.