library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.data_type_pkg.all; use work.common_functions_pkg.all; entity app_top is generic ( --! FPGA build ID (automatically set) g_ID : std_logic_vector(95 downto 0) := X"000000000000000000000000" ); port ( --! 125MHz clock i_clk : in std_logic; --! 250MHz clock i_clk2x : in std_logic; --! User clock i_usr_clk : in std_logic; --! User clock 2x i_usr_clk2 : in std_logic; --! Synchronous reset in the 125MHz clock domain i_rst : in std_logic; --! Synchronous reset in the 250MHz clock domain i_rst2x : in std_logic; --! Synchronous reset in the usr_clock domain i_usr_rst : in std_logic; --! Synchronous reset in the usr_clock_2 domain i_usr_rst2 : in std_logic; --! FPGA build ID (should be set to g_ID) o_ID : out std_logic_vector(95 downto 0) := g_ID; --! FPGA hardware time in 0.25ns resolution -------------------------------------------------------------- --!\name JTAG (connect to jtag_bridge_app to enable SignalTap) i_jtag_tck : in std_logic; i_jtag_tms : in std_logic; i_jtag_tdi : in std_logic; i_jtag_vir_tdi : in std_logic; i_jtag_ena : in std_logic; newSymbol : in std_logic; o_jtag_tdo : out std_logic := '0' ); end app_top; architecture behavior of app_top is component appIntegration is port ( clock_bridge_25mhz_in_clk : in std_logic := 'X'; -- clk clk_125_in_clk : in std_logic := 'X'; -- clk reset_25mhz_in_reset : in std_logic := 'X'; -- reset reset_125_in_reset : in std_logic := 'X' -- reset ); end component appIntegration; signal newSignal : std_logic_vector(99 downto 0); begin u0: component appIntegration port map ( clock_bridge_25mhz_in_clk => i_usr_clk, -- in std_logic := 'X'; -- clk clk_125_in_clk => i_clk, -- in std_logic := 'X'; -- clk reset_25mhz_in_reset => i_usr_rst, -- in std_logic := 'X'; -- reset reset_125_in_reset => i_rst -- in std_logic := 'X'; -- reset ); -- JTAG bridge (to allow SignalTap to be used) jtag0: entity work.jtag_bridge_app port map ( i_jtag_tck => i_jtag_tck, i_jtag_tms => i_jtag_tms, i_jtag_tdi => i_jtag_tdi, i_jtag_vir_tdi => i_jtag_vir_tdi, i_jtag_ena => i_jtag_ena, o_jtag_tdo => o_jtag_tdo ); end behavior;