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Archived Read Only Forums => SlickEdit 2014 v19 beta => Topic started by: tim_k on September 25, 2014, 09:29:20 pm

Title: B5: Syntax colorig/tagging of SystemVerilog
Post by: tim_k on September 25, 2014, 09:29:20 pm
The tagging/coloring of SystemVerilog files seems to have broken. Some ports get tagged & colored properly, while others don't. I haven't found a consistent behavior that says which will or won't get tagged properly. If I right-click on a port, and select "go to definition" I get a dialog that says "Tag <port name> not found", and the untagged ports are colored as unidentified symbols. This happens with parameters as well, but not with signals - they seem to work properly. Verilog, VHDL and TCL seem fine. Syntax coloring also seems slower than usual, even when it works.

It's broken in both Linux and MacOS versions.

I've tried going back to 2013 (Mac, 18.0.3.3) and opening the same files in the same workspace works fine, as expected.

I can provide simple sample code if desired.

-Tim
Title: Re: B5: Syntax colorig/tagging of SystemVerilog
Post by: Lee on September 25, 2014, 09:33:06 pm
If you have a concise sample demonstrating the issue you are encountering then please do post it.  We will take a look at it.
Title: Re: B5: Syntax colorig/tagging of SystemVerilog
Post by: tim_k on September 26, 2014, 08:18:26 pm
Here's a concise example. The symbols that are correctly colored/tagged are the module name 'test' , the input port 'reset_n', and the internal signal 'internalWord'. Nothing else is correctly handled. In 18.0.3.3, all are correctly tagged/colored. Language keywords seem to be OK.

-Tim

Example:

  `timescale 1ps/1ps

module test
  (
    input logic clock,
    input logic reset_n,
   
    input logic [15:0]  inputA,
    input logic [15:0]  inputB,
   
    output logic [15:0] outputA,
    output logic        validOut
  )
 
  logic [31:0]  internalWord;
 
  // flops

  always_ff @(posedge clock, negedge reset_n)
  begin
    if (!reset_n)
      begin
        outputA <= '0;
      end
    else
      begin
        outputA <= inputA && inputB;
      end
  end
 
endmodule
Title: Re: B5: Syntax colorig/tagging of SystemVerilog
Post by: Lee on September 26, 2014, 08:48:44 pm
Thanks for the sample, problem replicated and identified.  This will be fixed in the next drop.
Title: Re: B5: Syntax colorig/tagging of SystemVerilog
Post by: tim_k on September 26, 2014, 09:05:19 pm
Excellent! Thanks.

-Tim
Title: Re: B5: Syntax colorig/tagging of SystemVerilog
Post by: tim_k on September 30, 2014, 03:33:53 pm
Fix confirmed in B6.

-Tim