SlickEdit Community

SlickEdit Product Discussion => SlickEdit® => Topic started by: meidavec on May 22, 2015, 10:26:18 pm

Title: Begin/end style formatting option for Verilog language files
Post by: meidavec on May 22, 2015, 10:26:18 pm
How can I modify the begin/end style formatting for Verilog files?

In the SlickEdit options for "All Languages"->Formatting I can see begin/end "Style 3" which is exactly what we use (only in Verilog). This pane shows C style syntax:
    if()
        {
        ++i
        }

However in the Verilog language options, I don't see a similar setting, and certainly SlickEdit seems to automatically insert "Style 2" indents:
    if (condition)
    begin
        out = in;
    end

Is it possible for me to modify this syntax indent style?
Title: Re: Begin/end style formatting option for Verilog language files
Post by: patrick on May 26, 2015, 01:15:59 pm
There's no setting for that in Verilog/SystemVerilog.  This is scheduled to change in v20 though.