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Verilog Beautification : subset of system verilog
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Topic: Verilog Beautification : subset of system verilog (Read 2786 times)
cng18.1970
Junior Community Member
Posts: 3
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Verilog Beautification : subset of system verilog
«
on:
October 08, 2015, 04:08:12 AM »
Verilog beautification is a subset of systemVerilog beautification. Can it be made available along with systemverilog beautification. Maybe a switch to choose between verilog or systemverilog.
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patrick
SlickEdit Team Member
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Posts: 1818
Hero Points: 151
Re: Verilog Beautification : subset of system verilog
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Reply #1 on:
October 08, 2015, 01:11:21 PM »
That should be available in the beta 2 that's already out there. Beta 1 did not have it. But it looks like I didn't add that to the Readme for beta 2, sorry for the confusion.
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Verilog Beautification : subset of system verilog