RC-4 SystemVerilog beautifier 'align variables' inconsistent

[tim_k]

With the 'Align variables' option set in the beautifier format dialog, this is not fixed:

  logic [31:0]                          roiFrameBuffer0StartAddr;
  logic [31:0]                       roiFrameBuffer1StartAddr;
  logic [31:0]                          roiFrameBuffer2StartAddr;
  logic   [31:0]                         roiFrameBuffer3StartAddr;
  logic [31:0]                          roiStartOffset;


It should look like this:

  logic [31:0]                          roiFrameBuffer0StartAddr;
  logic [31:0]                          roiFrameBuffer1StartAddr;
  logic [31:0]                          roiFrameBuffer2StartAddr;
  logic [31:0]                          roiFrameBuffer3StartAddr;
  logic [31:0]                          roiStartOffset;


Or in isolation like this (this is part of a much larger list, with longer 'logic [...]' statements), the variables a space or tab off of the ']'.

-Tim

[patrick]

I've found a few contexts where the variables aren't being aligned.  (like in a typedef'd struct).  Just to make sure I'm not missing anything, where were you seeing these?

[tim_k]

These are just in a signals list at the beginning of the module...

module #(...)(....);
parameters ....
logic [...] signal;
many more then the rest of the logic, etc.

-Tim

[patrick]

As an update, I suspect this is a parser bug.   I've been adding more files to the regression tests, and have flushed out a couple of parse errors that can cause the signals list to not be aligned. 

So I'll clean these up and see if I find any others;  once it gets closer to point release time, I can send you some files and we can see if it's fixed with your source code.

[tim_k]

Sounds good. Anytime you want to test SystemVerilog, Verilog, or VHDL type things with a user, let me know.

-Tim.