Author Topic: Verilog: instantiations not visible in Defs pane?!?  (Read 5258 times)

Gyrfalcon

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Verilog: instantiations not visible in Defs pane?!?
« on: November 07, 2012, 01:35:20 am »
I'm hoping someone has the answer to this.

In most languages, Slick's Defs pane will show the relevant structural code items in a file, such as declarations, function calls etc.  Well much to my dismay I cannot find any way to get Slick to show module instantiations in Verilog!!  That seems like fairly basic functionality for a high-end editor, and without that, Slick becomes very limited.  Please tell me there's a way!  It certainly does so for VHDL instantiations...

Here's a Verilog example:
register_example  register1 (
    .rst_n                        (rst_n                ),
    .clk                            (clk                   )
);

Thank you kindly

chrisant

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Re: Verilog: instantiations not visible in Defs pane?!?
« Reply #1 on: November 07, 2012, 02:10:24 am »
I know very little about Verilog, but I found a few sample .v files in the interwebs, and SE seems to correctly do syntax coloring and show Defs in them.

In your example, SE flags "register_example" as an unknown symbol, and therefore also as an unknown keyword.  It appears to be used like a keyword in your example.

I couldn't find any mention of a "register_example" keyword in Verilog in the interwebs.

I don't know what to make of that.

Lee

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Re: Verilog: instantiations not visible in Defs pane?!?
« Reply #2 on: November 07, 2012, 01:32:18 pm »
Which version are you using and could you post a larger example?  There are some known parsing issues because SlickEdit does not have preprocessing support for Verilog.  But if you are not heavily using macros, there shouldn't be an issue. It should be showing module instantiations in the Defs panel.

Dennis

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Re: Verilog: instantiations not visible in Defs pane?!?
« Reply #3 on: November 07, 2012, 09:22:56 pm »
Make sure the source file in question is recognized as Verilog.  If you are using a non-standard file extension (something other than .v), this may be as simple as SlickEdit not being in Verilog mode.  Look at the Document menu and do Set Mode () if the file is not already recognized as Verilog.

Gyrfalcon

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Re: Verilog: instantiations not visible in Defs pane?!?
« Reply #4 on: November 09, 2012, 02:55:58 am »
Thanks all for your feedback.  I'm using SlickEdit 16.0.3, and my .v files are recognized as Verilog no problem.  Syntax highlighting and Defs work.  Not using any macros.

So I tried for the n'th time going through all the Defs possibilities (any way to toggle many at a time btw vs right-click/select each one?), and noticed the instantiations actually *were* there (Variables->Data Members -- my apologies), but unfortunately lost in the sea of "wire" and "reg" declarations.  It's unfortunate that 2 fundamentally different object types get amalgamated this way.  This is a general problem btw with the Slick Defs categories vs HDLs in general: the hard-coded software-oriented Defs categories don't map so well for HDLs.

Is there any way to "re-categorize" things in Def categories ?

Lastly, can Slick identify Verilog "always" blocks?  In Slick's VHDL, every "process" has a label and thus come up neatly in the Defs window which makes it really easy to navigate through source code.  Not so much in Verilog, so far as I can tell...?

Thanks in advance for any feedback and tips, I love slick for VHDL, tcl, C, and would love to keep using it for Verilog!
« Last Edit: November 09, 2012, 03:06:09 am by Gyrfalcon »

Dennis

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Re: Verilog: instantiations not visible in Defs pane?!?
« Reply #5 on: November 09, 2012, 01:33:23 pm »
You can download the trial of 17.0.2 to verify this, but I believe support for "always" blocks was added in the version 17 release.

I will file a feature request to add a new variable type for wires and regs (HDL Elements) and add the ability to filter them separately from other data members in the Defs tool window.

Gyrfalcon

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Re: Verilog: instantiations not visible in Defs pane?!?
« Reply #6 on: December 01, 2012, 04:10:16 am »
So I finally upgraded to 17.0.2, and didn't notice any difference for Verilog.  Always blocks don't seem to show up in Defs, nor do labelled begin/end blocks, such as the one shown below:

Code: [Select]
always @(posedge clk)
begin: this_is_a_label
  cha_d1                    <= cha;
  chb_d1                    <= chb;
end

I am also still curious about my other questions as well, if anyone has time to answer:
- Defs shown elements: any way to toggle many at a time vs right-click/select each one?
- Is there any way to "re-categorize" language elements in Def categories ?  Or is that hardcoded by the SlickEdit developers?  For example can I tell Slick that in Verilog, the keyword "always" should be categorized as a function.

Thanks!

Gyrfalcon

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Re: Verilog: instantiations not visible in Defs pane?!?
« Reply #7 on: December 07, 2012, 09:52:11 pm »
I am giving SlickEdit one last try before abandoning it for Verilog.  Are there any short-term plans to make it recognize "always" blocks as a structural element (akin to a function definition or something similar) that would show up in the Defs pane?

Otherwise SlickEdit becomes not much more than a colored-syntax editor when used with Verilog, which is hardly worth the price charged, given that many free editors do that already, and more...

Verilog doesn't appear to get much priority from the developers the way I see it... am I mistaken?

Thanks

Lee

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Re: Verilog: instantiations not visible in Defs pane?!?
« Reply #8 on: December 10, 2012, 02:43:30 pm »
I can add a feature request to make the always and initial blocks visible in the Defs view for the next release.

It's not that Verilog isn't a priority, sometimes it is more a function of not working day-to-day directly with a language.  We rely heavily on user feedback to help guide features to aid and assist developers.  This is especially true for languages that we ourselves don't use on a daily basis.  Feedback through the support channel and SlickEdit forums here are always welcome.

Gyrfalcon

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Re: Verilog: instantiations not visible in Defs pane?!?
« Reply #9 on: December 20, 2012, 12:09:45 am »
Ok I will try to keep providing feedback in the future.  Thanks for your replies!